1. Field of the Invention
The present invention relates to a charge pump circuit that produces a desired output voltage from an input voltage by turning on and off a plurality of charge transfer transistors periodically according to a clock signal and thereby charging and discharging a charge accumulation capacitor; the present invention also relates to an electric appliance provided with such a charge pump circuit.
2. Description of Related Art
FIG. 9 is a circuit diagram of an example of a conventional charge pump circuit. The charge pump circuit shown in the figure is so configured as to produce from an input voltage Vi a desired output voltage Vo (≧Vi) by turning on and off a plurality of charge transfer transistors Q1 to Q4 periodically according to a clock signal CLK (and an inverted clock signal CLKB) and thereby charging and discharging a charge accumulation capacitor C1. The output voltage Vo can be set freely in the range of −Vi≦Vo≦0.
Now, how this circuit outputs a negative voltage will be described specifically. To produce the output voltage Vo, first the transistors Q1 and Q3 are turned on, while the transistors Q2 and Q4 are left off. As a result of this switching, the input voltage Vi is applied through the transistor Q1 to one terminal (point A) of the capacitor C1; the other terminal (point B) of the capacitor C1 is grounded through the transistor Q3. This causes the capacitor C1 to be charged until the potential difference across it becomes equal to the input voltage Vi.
After the capacitor C1 is completely charged, now the transistors Q1 and Q3 are turned off, and the transistors Q2 and Q4 are turned on. As a result of this switching, point A is grounded through the transistor Q2. This causes the potential at point A to fall from the input voltage Vi down to the ground voltage GND. Here, as a result of the previous charging of the capacitor C1, a potential difference substantially equal to the input voltage Vi is present across the capacitor C1, and therefore, when the above-mentioned fall occurs in the potential at point A, the potential at point B falls from the ground voltage GND down to a negative voltage −Vi. Here, point B is conducting through the transistor Q4 to an output voltage extraction terminal, and thus the charge in the capacitor C1 moves to an output capacitor Co, causing the potential at the output voltage extraction terminal to fall down to the negative voltage −Vi.
A generally recognized disadvantage with the conventional charge pump circuit described above is the occurrence of rush currents that flow into the capacitor C1 at start-up (see FIG. 10). For this reason, in the charge pump circuit described above, device breakdown and excessive heat generation that may result from rush currents need to be prevented by the use of high-capacity transistors as Q1 to Q4. This counts as a factor hampering chip area reduction. As another disadvantage, the charge pump circuit needs to be fabricated by a process whose latch-up characteristics have been verified with large current. This unnecessarily limits the choice of feasible fabrication processes. As a further disadvantage, in a system involving a high-impedance power supply network, such as in a negative power supply in a hard disk drive, the occurrence of rush currents results in an insufficient supply voltage to the target appliance, making its operation unstable.
As a solution to these disadvantages, there have conventionally been proposed charge pump circuits in which rush currents into a capacitor are prevented by the use of a constant current circuit (for example, see JP-A-2005-057969).
Certainly, the conventional technology disclosed in JP-A-2005-057969 helps alleviate rush currents that occur at start-up.
Disadvantageously, however, this conventional technology requires provision of a constant current circuit in addition to charge transfer transistors Q1 to Q4 in the current path through the charge pump circuit. This increases the on-state resistance of the circuit as a whole, resulting in lower efficiency.